2015-04-27 PRACE PATC Course: Intel MIC&GPU Programming Workshop (HPGU1S15)
| Date: | Monday, April 27 - Wednesday, April 29, 2015, 9:00-18:00 |
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| Location: | LRZ Building, University campus Garching, near Munich |
| Contents: | With the rapidly growing demand for computing power new accelerator based architectures have entered the world of high performance computing since around 5 years. Particularly GPGPUs have recently become very popular, however programming GPGPUs using programming languages like CUDA or OpenCL is cumbersome and error-prone. Recently, Intel developed their own Many Integrated Core (MIC) architecture which can be programmed using standard parallel programming techniques like OpenMP and MPI. Since 2014, LRZ is running a new Intel Xeon Phi based system SuperMIC. This workshop is especially recommended for users who want to port their applications to SuperMIC or other Xeon Phi based systems. The course discusses various programming and optimisation techniques for Intel Xeon Phi in comparison with GPGPU programming techniques and includes several hands-on sessions on the new SuperMIC system at LRZ and on a GPU cluster. The course is developed in collaboration with the Erlangen Regional Computing Centre (RRZE) within KONWIHR. Tentative program: Day 1: GPGPU & MIC Programming Techniques
Day 2: Basic MIC Programming Methods
Day 3: Advanced MIC Programming
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| Prerequisites | Good working knowledge of at least one of the standard HPC languages: Fortran 95, C or C++. Basic OpenMP and MPI knowledge useful. |
| Language: | English |
| Teachers: | M. Allalen, V. Weinberg (LRZ), J. Eitzinger (RRZE), M. Klemm (Intel) |
| Registration: | Via the LRZ registration form (Please choose course HPGU1S15) |
| Contact: | Dr. Volker Weinberg (LRZ) |
| PATC-Webpage: | http://events.prace-ri.eu/e/LRZ-2015-HPGU1S15/ |