Most important Intel Compiler Options and Directives

SSE4.2: On the Westmeer Fat Nodes of SuperMUC Phase1: generate SSE4.2 instructions
AVX: On SandyBridge cores of the thin nodes of SuperMUC: generate Intel Advanced Vector Extensions.
CORE-AVX2: On Haswell cores of Phase2 of SuperMUC or on CollMUC2 of the Linux-Cluster: generate Advanced Vector Extensions 2.
MIC-AVX512: On the Knights Landing many-core nodes of the Linux-Cluster, may generate Advanced Vector Extensions 5
CORE-AVX512/COMMON-AVX512: On Skylake Nodes:  may generate Intel® Advanced Vector Extensions 512  

host: Tells the compiler to generate instructions for the highest instruction set available on the compilation host

-axcode1,code2

This option tells the compiler to generate multiple, processor-specific auto-dispatch code paths for Intel processors if there is a performance benefit. It also generates a baseline code path which can run on non-AVX processors. The Intel processor-specific auto-dispatch path is usually more optimized than the baseline path. May generate Intel(R) Advanced Vector Extensions 2 (AVX2), AVX, SSE4.2,  SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel(R) processors.
The  option  tells  the compiler to find opportunities to generate separate versions of functions that take advantage of features of the specified instruction features. If the compiler finds such an opportunity, it first checks whether generating a feature-specific version of a function is likely to result in a performance gain. If this is the case, the compiler generates both a feature-specific version of a function and a baseline version of the function. At run time, one of the versions is chosen to execute, depending on the Intel(R) processor in use.
Three version will be generated with -axAVX,CORE-AVX2: baseline, Sandy-Bridge and Haswell.