2016-06-27 PRACE PATC Course: Intel MIC Programming Workshop

The course discusses Intel’s new Many Integrated Core (MIC) architecture. It covers various programming and optimisation techniques for Intel Xeon Phi coprocessors.

The first 2 days provide an introduction about the Intel MIC architecture and various Intel Xeon Phi programming models, interleaved with many hands-on sessions. The hands-on sessions are done on the SuperMIC system at LRZ.

The last day presents advanced topics and talks about experiences and best practices using Intel Xeon Phi based systems like e.g. Salomon @ IT4Innovations (Czech Republic), the largest Intel Xeon Phi based system in Europe.

Please bring your own laptop (with an ssh client installed) for the hands-on sessions!

Tentative Agenda

Monday, June  27,  2016, Seminarraum 1, H.E.008

• 09:00-10:00 Introduction (Weinberg)
• 10:00-10:30 Hardware Overview and Native I (Allalen)
• 10:30-11:00 Coffee Break
• 11:00-11:30 Hardware Overview and Native II (Allalen)
• 11:30-12:00 Lab: Native Mode
• 12:00-13:00 Lunch Break
• 13:00-14:00 Offloading Part I (Weinberg)
• 14:00-15:00 Lab: Offloading I
• 15:00-15:30 Coffee Break
• 15:30-16:15 Offloading Part II (Weinberg)
• 16:15-17:00 Lab: Offloading II

Tuesday, June  28,  2016,  Seminarraum 1, H.E.008

• 09:00-09:30 MPI (Weinberg)
• 09:30-10:30 Lab: MPI
• 10:30-11:00 Coffee Break
• 11:00-11:30 MKL (Allalen)
• 11:30-12:00 Lab: MKL I
• 12:00-13:00 Lunch break
• 13:00-13:30 Lab: MKL II
• 13:30-14:00 Vectorisation & Performance (Allalen)
• 14:00-15:00 Lab: Vectorisation
• 15:00-15:30 Coffee Break
• 15:30-17:30 Tools for Intel Xeon Phi (Baruffa)

• 18:00 Bus leaving in front of main entrance for social event: Guided tour of Weihenstephan Brewery and dinner
• 22:00 Bus leaving at Weihenstephan

Wednesday, June  29,  2016, 09:00-12:00, Hörsaal, H.E.009 (Lecture Hall), public session

• 09:00-10:30 Advanced MIC Programming Techniques (SIMD, Intrinsics,... ) (Jan Eitzinger, RRZE)
• 10:30-10:45 Coffee Break
• 10:45-12:00 Knights Landing (KNL) architecture and software (Andrey Semin, Intel)
• 12:00-13:00 Lunch break

Wednesday, June  29,  2016, 13:00-18:00, Hörsaal, H.E.009 (Lecture Hall)

Plenum session with invited talks on MIC experience and best practice recommendations
(joint session with the Scientific Workshop "High Performance Computing for Water Related Hazards"), public session

• 13:00-13:45 Andrey Semin, Intel: "Intel Xeon Phi (Knights Landing) optimisation best known methods"
• 13:45-14:30 Jan Eitzinger, RRZE: "Evaluation of Intel Xeon Phi "Knights Corner": Opportunities and Shortcomings"

• 14:30-14:45 Coffee Break

• 14:45-15:30 Serhiy Mochalskyy, IPP: "Simulation using MIC co-processor on HELIOS"
• 15:30-16:15 Vit Vondrak, IT4Innovations: "ESPRESO solver based on hybrid FETI method on MIC architecture"

• 16:15-16:30 Coffee Break

• 16:30-17:15 Michael Bader, IPCC@TUM: "Experiences with earthquake and tsunami simulation on Xeon Phi platforms"
• 17:15-18:00 Luigi Iapichino / Fabio Baruffa, IPCC@LRZ: "Towards modernisation of the Gadget code on many-core architectures"

The course material is developed within PRACE and the joint German-Czech Republic project CzeBaCCA. The plenum session is also part of a three-day scientific workshop on "High Performance Computing for Water Related Hazards" of this project taking place at LRZ on June 29 - July 1, 2016.

See https://www.lrz.de/services/compute/courses/2016-06-29_hwrh1s16/

The course is a PRACE Advanced Training Center event.

A social event for participant and instructor networking is planned for the evening on Tuesday 28 June (tbc), consisting of a guided tour of the Weihenstephan Brewery followed by a self-paid dinner at the brewery restaurant.

Acknowledgements